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Nuvoton /M05x_registers /TMR0 /TISR

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Interpret as TISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIF)TIF

Description

Timer0 Interrupt Status Register

Fields

TIF

Timer Interrupt Flag This bit indicates the interrupt status of Timer. TIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data