UART0 FIFO Control Register.
| RFR | Rx Software Reset When Rx_RST is set, all the bytes in the transmit FIFO and Rx internal state machine are cleared. 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit will reset the Rx internal state machine and pointers. Note: This bit will auto clear and takes at least 3 UART engine clock cycles. |
| TFR | Tx Software Reset When Tx_RST is set, all the bytes in the transmit FIFO and Tx internal state machine are cleared. 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit will reset the Tx internal state machine and pointers. Note: This bit will auto clear and takes at least 3 UART engine clock cycles. |
| RFITL | Word Length Select RFITL INTR_RDA Tigger Level(Bytes) 0000 01 0001 04 0010 08 0011 14 |
| RX_DIS | Receiver Disable register. The receiver is disabled or not (set 1 is disable receiver) 1: Disable Receiver 0: Enable Receiver Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485 enable function in UA_FUN_SEL. FUN_SEL is programmed. |
| RTS_Tri_Lev | Word Length Select RTS_Tri_Lev Trigger Level(Bytes) 0000 01 0001 04 0010 08 0011 14 |