A/D Data Register 7
| RSLT | A/D Conversion Result This field contains conversion result of ADC. For Medium density, RSLT[15:12] always read as 0. For Low density, if DMOF bit (ADCR[31]) set to 0, 12 bits ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12]. If DMOF bit (ADCR[31]) set to 1, 12 bits ADC conversion result with 2’s complement format will be filled in RSLT[11:0] and signed bits will be filled in RSLT[15:12]. |
| OVERRUN | Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It will be cleared by hardware after ADDR register is read. |
| VALID | Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read. |