Clock Divider Number Register
| HCLK_N | HCLK clock divide number from HCLK clock source The HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1) |
| USB_N | USB clock divide number from PLL clock The USB clock frequency = (PLL frequency ) / (USB_N + 1) |
| UART_N | UART clock divide number from UART clock source The UART clock frequency = (UART clock source frequency ) / (UART_N + 1) |
| CAN_N_L | CAN clock divide number from CAN clock source The CAN clock frequency = (CAN clock source frequency ) / (CAN_N + 1) Which CAN_N = 16 * CAN_N_H + CAN_N_L |
| ADC_N | ADC clock divide number from ADC clock source The ADC clock frequency = (ADC engine clock source frequency ) / (ADC_N + 1) |
| CAN_N_H | CAN clock divide number from CAN clock source (Low Density Only) The CAN clock frequency = (CAN clock source frequency ) / (CAN_N + 1) Which CAN_N = 16 * CAN_N_H + CAN_N_L |