Clock status monitor Register
| XTL12M_STB | XTL12M clock source stable flag 1 = XTL12M clock is stable 0 = XTL12M clock is not stable or disabled This is read only bit |
| XTL32K_STB | XTL32K clock source stable flag 1 = XTL32K clock is stable 0 = XTL32K clock is not stable or disabled This is read only bit |
| PLL_STB | PLL clock source stable flag 1 = PLL clock is stable 0 = PLL clock is not stable or disabled This is read only bit |
| OSC10K_STB | OSC10K clock source stable flag 1 = OSC10K clock is stable 0 = OSC10K clock is not stable or disabled This is read only bit |
| OSC22M_STB | OSC22M clock source stable flag 1 = OSC22M clock is stable 0 = OSC22M clock is not stable or disabled This is read only bit |
| CLK_SW_FAIL | Clock switching fail flag 1 = Clock switching failure 0 = Clock switching success This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 1’b0. If switch target clock is not stable, this bit will be set to 1’b1. Write 1 to clear the bit to zero |