Nuvoton /NUC1xx_registers /CLK /PLLCON

PLL Feedback Divider Control Pins Refer to the formulas below the table. FOUT = FIN x NF/NR x 1/NO Constrain:

1. 3.2MHz < FIN < 150MHz
2. 800KHz < FIN/(2xNR) < 8MHz
3. 100MHz < FCO = FINxNF/NR < 200MHz , 120M < FCO is preferred. Symbol Description FOUT Output Clock Frequency FIN Input (Reference) Clock Frequency NR Input Divider (IN_DV + 2) NF Feedback Divider (FB_DV + 2) NO OUT_DV = “00”:NO = 1 OUT_DV = “01”:NO = 2 OUT_DV = “10”:NO = 2 OUT_DV = “11”:NO = 4

PLL Input Divider Control Pins Refer to the formulas below the table. (Table is the same as FB_DV).

PLL Output Divider Control Pins Refer to the formulas below the table. (Table is the same as FB_DV).

Power Down Mode. If set the IDLE bit “1” in PWRCON register, the PLL will enter power down mode too 0 = PLL is in normal mode 1 = PLL is in power-down mode(default)

PLL Bypass Control 0 = PLL is in normal mode (default) 1 = PLL clock output is same as clock input (XTALin)

PLL OE (FOUT enable) pin Control 0 = PLL FOUT enable 1 = PLL FOUT is fixed low

PLL Source Clock Select 1 = PLL source clock from 22.1184 MHz oscillator 0 = PLL source clock from 4~24 MHz crystal