Nuvoton /NUC1xx_registers /CLK /PWRCON

External 4~24 MHz Crystal Enable (write-protection bit) The bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz crystal, this bit is set to 1 automatically 1 = Enable external 4~24 MHz crystal 0 = Disable external 4~24 MHz crystal

External 32.768 KHz Crystal Enable (write-protection bit) 1 = Enable external 32.768 kHz Crystal (Normal operation) 0 = Disable external 32.768 kHz Crystal

Internal 22.1184MHz Oscillator Enable (write-protection bit) 1 = Enable 22.1184MHz Oscillation 0 = Disable 22.1184MHz Oscillation

Internal 10KHz Oscillator Enable (write-protection bit) 1 = Enable 10KHz Oscillation 0 = Disable 10KHz Oscillation

Enable the wake up delay counter (write-protection bit) When the chip wakes up from power down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz crystal, and 256 clock cycles when chip work at internal 22.1184 MHz oscillator. 1 = Enable clock cycles delay 0 = Disable clock cycles delay

Power down mode wake up Interrupt enable (write-protection bit) 0 = Disable 1 = Enable. The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.

Power down mode wake up interrupt status Set by “power down wake up”, it indicates that resume from power down mode The flag is set if the GPIO, USB, UART, WDT, CAN, ACMP, BOD or RTC wakeup occurred Write 1 to clear the bit Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.

System power down enable bit (write-protection bit) When CPU sets this bit “1” the chip power down mode is enabled, and chip power-down behavior will depends on the PD_WAIT_CPU bit. (a) If the PD_WAIT_CPU is “0”, then the chip enters power down mode immediately after the PWR_DOWN_EN bit set. (b) if the PD_WAIT_CPU is “1”, then the chip keeps active till the CPU sleep mode is also active and then the chip enters power down mode. When chip wakes up from power down mode, this bit is auto cleared. Users need to set this bit again for next power down. When in power down mode, external 4~24 MHz crystal and the internal 22.1184 MHz oscillator will be disabled in this mode, but the external 32 kHz crystal and internal 10 kHz oscillator are not controlled by power down mode. When in power down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by power down mode, if the peripheral clock source is from 32 kHz crystal or the 10 kHz oscillator. 1 = Chip enter the power down mode instant or wait CPU sleep command WFI. 0 = Chip operate in normal mode or CPU in idle mode (sleep mode) because of WFI command.

This bit control the power down entry condition (write-protection bit) 1 = Chip enter power down mode when the both PWR_DOWN_EN bit is set to 1 and CPU run WFI instruction. 0 = Chip entry power down mode when the PWR_DOWN_EN bit is set to 1.