Nuvoton /NUC1xx_registers /GCR /REGWRPROT

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Interpret as REGWRPROT

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0REGWRPROT

Description

Register Write Protect Register

Fields

REGPROTDIS

Register Write Protection Disable Index (Read only) 1 = Write-Protection is disabled for writing protected registers 0 = Write-Protection is enabled for writing protected registers. Any write to the protected register is ignored. The Protected registers are: IPRST1: address 0x5000_0008 BODCR: address 0x5000_0018 PORCR: address 0x5000_0024 PWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) APBCLK bit[0]: address 0x5000_0208 (bit[0] is watchdog timer clock enable) CLK_SEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select) CLK_SEL1 bit[1:0]: address 0x5000_0214 (for watch dog clock source select) ISPCON: address 0x5000_C000 (Flash ISP Control register) WTCR: address 0x4000_4000 FATCON: address 0x5000_C018

REGWRPROT

Register Write-Protection Code (Write only) Some write-protected registers have to be disabled the protected function by writing the sequence value “59h”, “16h”, “88h” to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protected registers can be normal write.

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