I2S Clock Divider Register
| MCLK_DIV | Master Clock Divider If chip external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLK_DIV is set to 0, MCLK is the same as external clock input. For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLK_DIV=1. F_MCLK = F_I2SCLK/(2x(MCLK_DIV)) (When MCLK_DIV is >= 1 ) F_MCLK = F_I2SCLK (When MCLK_DIV is set to 0 ) |
| BCLK_DIV | Bit Clock Divider If I2S operates in master mode, bit clock is provided by NuMicro™ NUC100 series. Software can program these bits to generate sampling rate clock frequency. F_BCLK = F_I2SCLK /(2x(BCLK_DIV + 1)) |