I2S Control Register
| I2SEN | Enable I2S Controller 1 = Enable 0 = Disable |
| TXEN | Transmit Enable 1 = Enable data transmit 0 = Disable data transmit |
| RXEN | Receive Enable 1 = Enable data receive 0 = Disable data receive |
| MUTE | Transmit Mute Enable 1 = Transmit channel zero 0 = Transmit data is shifted from buffer |
| WORDWIDTH | Word Width 00 = data is 8 bit 01 = data is 16 bit 10 = data is 24 bit 11 = data is 32 bit |
| MONO | Monaural Data 1 = Data is monaural format 0 = Data is stereo format |
| FORMAT | Data Format 1 = MSB justified data format 0 = I2S data format |
| SLAVE | Slave Mode I2S can operate as master or slave. For master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro™ NUC100 series to Audio CODEC chip. In slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip. 1 = Slave mode 0 = Master mode |
| TXTH | Transmit FIFO Threshold Level If remain data word (32 bits) in transmit FIFO is the same or less than threshold level then TXTHI flag is set. 000 = 0 word data in transmit FIFO 001 = 1 word data in transmit FIFO 010 = 2 words data in transmit FIFO 011 = 3 words data in transmit FIFO 100 = 4 word data in transmit FIFO 101 = 5 word data in transmit FIFO 110 = 6 word data in transmit FIFO 111 = 7 word data in transmit FIFO |
| RXTH | Receive FIFO Threshold Level When received data word(s) in buffer is equal or higher than threshold level then RXTHI flag is set. 000 = 1 word data in receive FIFO 001 = 2 word data in receive FIFO 010 = 3 word data in receive FIFO 011 = 4 word data in receive FIFO 100 = 5 word data in receive FIFO 101 = 6 word data in receive FIFO 110 = 7 word data in receive FIFO 111 = 8 word data in receive FIFO |
| MCLKEN | Master Clock Enable If NuMicro™ NUC100 series external crystal clock is frequency 2N256fs then software can program MCLK_DIV[2:0] in I2S_CLKDIV register to get 256fs clock to audio codec chip. 1 = Enable master clock 0 = Disable master clock |
| RCHZCEN | Right channel zero cross detect enable If this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then RZCF flag in I2S_STATUS register is set to 1. 1 = Enable right channel zero cross detect 0 = Disable right channel zero cross detect |
| LCHZCEN | Left channel zero cross detect enable If this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to 1. 1 = Enable left channel zero cross detect 0 = Disable left channel zero cross detect |
| CLR_TXFIFO | Clear Transmit FIFO Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXFIFO_LEVEL[3:0] returns to zero and transmit FIFO becomes empty but data in transmit FIFO is not changed. This bit is clear by hardware automatically, read it return zero. |
| CLR_RXFIFO | Clear Receive FIFO Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXFIFO_LEVEL[3:0] returns to zero and receive FIFO becomes empty. This bit is clear by hardware automatically, read it return zero. |
| TXDMA | Enable Transmit DMA When TX DMA is enabled, I2S requests DMA to transfer data from SRAM to transmit FIFO if FIFO is not full. 1 = Enable TX DMA 0 = Disable TX DMA |
| RXDMA | Enable Receive DMA When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty. 1 = Enable RX DMA 0 = Disable RX DMA |