Nuvoton /NUC1xx_registers /I2S /I2S_IE

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Interpret as I2S_IE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXUDFIE)RXUDFIE 0 (RXOVFIE)RXOVFIE 0 (RXTHIE)RXTHIE 0 (TXUDFIE)TXUDFIE 0 (TXOVFIE)TXOVFIE 0 (TXTHIE)TXTHIE 0 (RZCIE)RZCIE 0 (LZCIE)LZCIE

Description

I2S Interrupt Enable Register

Fields

RXUDFIE

Receive FIFO underflow interrupt enable If software read receive FIFO when it is empty then RXUDF flag in I2SSTATUS register is set to 1. 1 = Enable interrupt 0 = Disable interrupt

RXOVFIE

Receive FIFO overflow interrupt enable 1 = Enable interrupt 0 = Disable interrupt

RXTHIE

Receive FIFO threshold level interrupt When data word in receive FIFO is equal or higher then RXTH[2:0] and the RXTHI bit is set to 1. If RXTHIE bit is enabled, interrupt occur. 1 = Enable interrupt 0 = Disable interrupt

TXUDFIE

Transmit FIFO underflow interrupt enable Interrupt occurs if this bit is set to 1 and transmit FIFO underflow flag is set to 1. 1 = Enable interrupt 0 = Disable interrupt

TXOVFIE

Transmit FIFO overflow interrupt enable Interrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1. 1 = Enable interrupt 0 = Disable interrupt

TXTHIE

Transmit FIFO threshold level interrupt enable Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0]. 1 = Enable interrupt 0 = Disable interrupt

RZCIE

Right channel zero cross interrupt enable Interrupt occurs if this bit is set to 1 and right channel zero cross. 1 = Enable interrupt 0 = Disable interrupt

LZCIE

Left channel zero cross interrupt enable Interrupt occurs if this bit is set to 1 and left channel zero cross. 1 = Enable interrupt 0 = Disable interrupt

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