Nuvoton /NUC1xx_registers /I2S /I2S_STATUS

I2S Interrupt flag 1 = I2S interrupt 0 = No I2S interrup It is wire-OR of I2STXINT and I2SRXINT bits. This bit is read only.

I2S receive interrupt 1 = Receive interrupt 0 = No receive interrupt This bit is read only

I2S transmit interrupt 1 = Transmit interrupt 0 = No transmit interrupt This bit is read only

Right channel This bit indicate current transmit data is belong to right channel. 1 = Right channel 0 = Left channel This bit is read only.

Receive FIFO underflow flag Read receive FIFO when it is empty, this bit set to 1 indicate underflow occur. 1 = Underflow occur 0 = No underflow occur Write 1 to clear this bit.

Receive FIFO overflow flag When receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote. 1 = Overflow occur 0 = No overflow occur Write 1 to clear this bit.

Receive FIFO threshold flag When data word(s) in receive FIFO is equal or higher than threshold value set in RXTH[2:0] the RXTHF bit becomes to 1. It keeps at 1 till RXFIFO_LEVEL[3:0] less than RXTH[1:0] after software read RXFIFO register. 1 = Data word(s) in FIFO is equal or higher than threshold level 0 = Data word(s) in FIFO is lower than threshold level This bit is read only.

Receive FIFO full This bit reflect data words number in receive FIFO is 8. 1 = Full 0 = Not full This bit is read only.

Receive FIFO empty This bit reflects data words number in receive FIFO is zero. 1 = Empty 0 = Not empty This bit is read only.

Transmit FIFO underflow flag When transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1. 1 = Underflow 0 = No underflow Software can write 1 to clear this bit.

Transmit FIFO overflow flag Write data to transmit FIFO when it is full and this bit set to 1. 1 = Overflow 0 = No overflow Software can write 1 to clear this bit.

Transmit FIFO threshold flag When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH[2:0] the TXTHF bit becomes to 1. It keeps at 1 till TXFIFO_LEVEL[3:0] is higher than TXTH[1:0] after software write TXFIFO register. 1 = Data word(s) in FIFO is equal or lower than threshold level 0 = Data word(s) in FIFO is higher than threshold level This bit is read only.

Transmit FIFO full This bit reflect data word number in transmit FIFO is 8. 1 = Full 0 = Not full This bit is read only.

Transmit FIFO empty This bit reflect data word number in transmit FIFO is zero. 1 = Empty 0 = Not empty This bit is read only.

Transmit Busy This bit is clear to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer. 1 = Transmit shift buffer is busy 0 = Transmit shift buffer is empty This bit is read only.

Right channel zero cross flag It indicates right channel next sample data sign bit is changed or all data bits are zero. 1 = Right channel zero cross is detected 0 = No zero cross Software can write 1 to clear this bit to zero.

Left channel zero cross flag It indicates left channel next sample data sign bit is changed or all data bits are zero. 1 = Left channel zero cross is detected 0 = No zero cross Software can write 1 to clear this bit to zero.

Receive FIFO level These bits indicate word number in receive FIFO. 0000 = No data 0001 = 1 word in receive FIFO 0010 = 2 word in receive FIFO 0011 = 3 word in receive FIFO 0100 = 4 word in receive FIFO 0101 = 5 word in receive FIFO 0110 = 6 word in receive FIFO 0111 = 7 word in receive FIFO 1000 = 8 word in receive FIFO

Transmit FIFO level These bits indicate word number in Transmit FIFO. 0000 = No data 0001 = 1 word in Transmit FIFO 0010 = 2 word in Transmit FIFO 0011 = 3 word in Transmit FIFO 0100 = 4 word in Transmit FIFO 0101 = 5 word in Transmit FIFO 0110 = 6 word in Transmit FIFO 0111 = 7 word in Transmit FIFO 1000 = 8 word in Transmit FIFO