PDMA Control and Status Register CHx
| PDMACEN | PDMA Channel Enable Setting this bit to 1 enables PDMA’s operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. Note: SW_RST(PDMA_CSRx[1], x= 0~8) will clear this bit. |
| SW_RST | Software Engine Reset 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit will reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will auto clear after few clock cycles. |
| MODE_SEL | PDMA Mode Select 00 = Memory to Memory mode (Memory-to-Memory). 01 = IP to Memory mode (APB-to-Memory). 10 = Memory to IP mode (Memory-to-APB). |
| SAD_SEL | Transfer Source Address Direction Select 00 = Transfer Source address is incremented successively. 01 = Reserved. 10 = Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations). 11 = Reserved. |
| DAD_SEL | Transfer Destination Address Direction Select 00 = Transfer Destination address is incremented successively. 01 = Reserved. 10 = Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination). 11 = Reserved. |
| APB_TWS | Peripheral transfer Width Select 00 = One word (32 bits) is transferred for every PDMA operation. 01 = One byte (8 bits) is transferred for every PDMA operation. 10 = One half-word (16 bits) is transferred for every PDMA operation. 11 = Reserved. Note: This field is meaningful only when MODE_SEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB). |
| TRIG_EN | Trig_EN 0 = No effect. 1 = Enable PDMA data read or write transfer. Note: When PDMA transfer completed, this bit will be cleared automatically. If the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. |