Nuvoton /NUC1xx_registers /PDMA_GCR /PDMA_GCRISR

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Interpret as PDMA_GCRISR

Description

PDMA Global Interrupt Register

Fields

INTR0	Interrupt Pin Status of Channel 0 This bit is the Interrupt pin status of PDMA channel0. Note: This bit is read only
INTR1	Interrupt Pin Status of Channel 1 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel1. Note: This bit is read only
INTR2	Interrupt Pin Status of Channel 2 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel2. Note: This bit is read only
INTR3	Interrupt Pin Status of Channel 3 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel3. Note: This bit is read only
INTR4	Interrupt Pin Status of Channel 4 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel4. Note: This bit is read only
INTR5	Interrupt Pin Status of Channel 5 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel5. Note: This bit is read only
INTR6	Interrupt Pin Status of Channel 6 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel 6. Note: This bit is read only
INTR7	Interrupt Pin Status of Channel 7 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel 7. Note: This bit is read only
INTR8	Interrupt Pin Status of Channel 4 (Medium Density Only) This bit is the Interrupt pin status of PDMA channel 8. Note: This bit is read only
INTR	Interrupt Pin Status This bit is the Interrupt pin status of PDMA controller. Note: This bit is read only

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