PS2 Control Register
| PS2EN | Enable PS2 Device Enable PS2 device controller 1 = Enable 0 = Disable |
| TXINTEN | Enable Transmit Interrupt 1 = Enable data transmit complete interrupt 0 = Disable data transmit complete interrupt |
| RXINTEN | Enable Receive Interrupt 1 = Enable data receive complete interrupt 0 = Disable data receive complete interrupt |
| TXFIFO_DEPTH | Transmit Data FIFO Depth There is 16 bytes buffer for data transmit. S/W can define the FIFO depth from 1 to 16 bytes depends on application. 0 = 1 byte 1 = 2 bytes … 14 = 15 bytes 15 = 16 bytes |
| ACK | Acknowledge Enable 1 = If parity error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock 0 = Always send acknowledge to host at 12th clock for host to device communication. |
| CLRFIFO | Clear TX FIFO Write 1 to this bit to terminate device to host transmission. The TXEMPTY bit in PS2STATUS bit will be set to 1 and pointer BYTEIDEX is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been cleared. 1 = Clear FIFO 0 = Not active |
| OVERRIDE | Software Override PS2 CLK/DATA Pin State 1 = PS2CLK and PS2DATA pins are controlled by S/W 0 = PS2CLK and PS2DATA pins are controlled by internal state machine. |
| FPS2CLK | Force PS2CLK Line It forces PS2CLK line high or low regardless of the internal state of the device controller if OVERRIDE is set to high. 1 = Force PS2DATA line high 0 = Force PS2DATA line low |
| FPS2DAT | Force PS2DATA Line It forces PS2DATA high or low regardless of the internal state of the device controller if OVERRIDE is set to high. 1 = Force PS2DATA high 0 = Force PS2DATA low |