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Nuvoton /NUC1xx_registers /PS2 /PS2INTID

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Interpret as PS2INTID

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXINT)RXINT 0 (TXINT)TXINT

Description

PS2 Interrupt Identification Register

Fields

RXINT

Receive Interrupt This bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXINTEN bit is set to 1. 1 = Receive interrupt occurs 0 = No interrupt Write 1 to clear this bit to 0.
TXINT

Transmit Interrupt This bit is set to 1 after STOP bit is transmitted. Interrupt occur if TXINTEN bit is set to 1. 1 = Transmit interrupt occurs 0 = No interrupt Write 1 to clear this bit to 0.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data