PS2 Status Register
| PS2CLK | CLK Pin State This bit reflects the status of the PS2CLK line after synchronizing. |
| PS2DATA | DATA Pin State This bit reflects the status of the PS2DATA line after synchronizing and sampling. |
| FRAMERR | Frame Error For host to device communication, if STOP bit (logic 1) is not received it is a frame error. If frame error occurs, DATA line may keep at low state after 12th clock. At this moment, S/w overrides PS2CLK to send clock till PS2DATA release to high state. After that, device sends a “Resend” command to host. 1 = Frame error occur 0 = No frame error Write 1 to clear this bit. |
| RXPARITY | Received Parity This bit reflects the parity bit for the last received data byte (odd parity). Read only bit. |
| RXBUSY | Receive Busy This bit indicates that the PS2 device is currently receiving data. 0 = Idle. 1 = Currently receiving data. Read only bit. |
| TXBUSY | Transmit Busy This bit indicates that the PS2 device is currently sending data. 0 = Idle. 1 = Currently sending data. Read only bit. |
| RXOVF | RX Buffer Overwrite 1 = Data in PS2RXDATA register is overwritten by new coming data. 0 = No overwrite Write 1 to clear this bit. |
| TXEMPTY | TX FIFO Empty When S/W writes any data to PS2TXDATA0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is clear to 1. 1 = FIFO is empty 0 = There is data to be transmitted Read only bit. |
| BYTEIDX | Byte Index It indicates which data byte in transmit data shift register. When all data in FIFO is transmitted and it will be cleared to 0. It is a read only bit. BYTEIDX DATA Transmit BYTEIDX DATA Transmit 0000 TXDATA0[7:0] 1000 TXDATA2[7:0] 0001 TXDATA0[15:8] 1001 TXDATA2[15:8] 0010 TXDATA0[23:16] 1010 TXDATA2[23:16] 0011 TXDATA0[31:24] 1011 TXDATA2[31:24] 0100 TXDATA1[7:0] 1100 TXDATA3[7:0] 0101 TXDATA1[15:8] 1101 TXDATA3[15:8] 0110 TXDATA1[23:16] 1110 TXDATA3[23:16] 0111 TXDATA1[31:24] 1111 TXDATA3[31:24] |