Capture Control Register 0
| INV0 | Channel 0 Inverter Enable 1 = Inverter enable. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter disable |
| CRL_IE0 | Channel 0 Rising Latch Interrupt Enable 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 0 has rising transition, Capture issues an Interrupt. |
| CFL_IE0 | Channel 0 Falling Latch Interrupt Enable 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 0 has falling transition, Capture issues an Interrupt. |
| CAPCH0EN | Channel 0 Capture Function Enable 1 = Enable capture function on PWM group channel 0. 0 = Disable capture function on PWM group channel 0. When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt. |
| CAPIF0 | Channel 0 Capture Interrupt Indication Flag If PWM group channel 0 rising latch interrupt is enabled (CRL_IE0=1), a rising transition occurs at PWM group channel 0 will result in CAPIF0 to high; Similarly, a falling transition will cause CAPIF0 to be set high if PWM group channel 0 falling latch interrupt is enabled (CFL_IE0=1). Write 1 to clear this bit to zero |
| CRLRI0 | CRLR0 Latched Indicator Bit When PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1. |
| CFLRI0 | CFLR0 Latched Indicator Bit When PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1. |
| INV1 | Channel 1 Inverter Enable 1 = Inverter enable. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter disable |
| CRL_IE1 | Channel 1 Rising Latch Interrupt Enable 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 1 has rising transition, Capture issues an Interrupt. |
| CFL_IE1 | Channel 1 Falling Latch Interrupt Enable 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 1 has falling transition, Capture issues an Interrupt. |
| CAPCH1EN | Channel 1 Capture Function Enable 1 = Enable capture function on PWM group channel 1. 0 = Disable capture function on PWM group channel 1. When Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt. |
| CAPIF1 | Channel 1 Capture Interrupt Indication Flag If PWM group channel 1 rising latch interrupt is enabled (CRL_IE1=1), a rising transition occurs at PWM group channel 1 will result in CAPIF1 to high; Similarly, a falling transition will cause CAPIF1 to be set high if PWM group channel 1 falling latch interrupt is enabled (CFL_IE1=1). Write 1 to clear this bit to zero |
| CRLRI1 | CRLR1 Latched Indicator Bit When PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1. |
| CFLRI1 | CFLR1 Latched Indicator Bit When PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1. |