Capture Control Register 2
| INV2 | Channel 2 Inverter Enable 1 = Inverter enable. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter disable |
| CRL_IE2 | Channel 2 Rising Latch Interrupt Enable 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt. |
| CFL_IE2 | Channel 2 Falling Latch Interrupt Enable 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 2 has falling transition, Capture issues an Interrupt. |
| CAPCH2EN | Channel 2 Capture Function Enable 1 = Enable capture function on PWM group channel 2. 0 = Disable capture function on PWM group channel 2. When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt. |
| CAPIF2 | Channel 2 Capture Interrupt Indication Flag If PWM group channel 2 rising latch interrupt is enabled (CRL_IE2=1), a rising transition occurs at PWM group channel 2 will result in CAPIF2 to high; Similarly, a falling transition will cause CAPIF2 to be set high if PWM group channel 2 falling latch interrupt is enabled (CFL_IE2=1). Write 1 to clear this bit to zero |
| CRLRI2 | CRLR2 Latched Indicator Bit When PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1. |
| CFLRI2 | CFLR2 Latched Indicator Bit When PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1. |
| INV3 | Channel 3 Inverter Enable 1 = Inverter enable. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter disable |
| CRL_IE3 | Channel 3 Rising Latch Interrupt Enable 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 3 has rising transition, Capture issues an Interrupt. |
| CFL_IE3 | Channel 3 Falling Latch Interrupt Enable 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 3 has falling transition, Capture issues an Interrupt. |
| CAPCH3EN | Channel 3 Capture Function Enable 1 = Enable capture function on PWM group channel 3. 0 = Disable capture function on PWM group channel 3. When Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt. |
| CAPIF3 | Channel 3 Capture Interrupt Indication Flag If PWM group channel 3 rising latch interrupt is enabled (CRL_IE3=1), a rising transition occurs at PWM group channel 3 will result in CAPIF3 to high; Similarly, a falling transition will cause CAPIF3 to be set high if PWM group channel 3 falling latch interrupt is enabled (CFL_IE3=1). Write 1 to clear this bit to zero |
| CRLRI3 | CRLR3 Latched Indicator Bit When PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1. |
| CFLRI3 | CFLR3 Latched Indicator Bit When PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1. |