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Nuvoton /NUC1xx_registers /PWMA /PIIR

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Interpret as PIIR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PWMIF0)PWMIF0 0 (PWMIF1)PWMIF1 0 (PWMIF2)PWMIF2 0 (PWMIF3)PWMIF3

Description

PWM Interrupt Indication Register

Fields

PWMIF0

PWM Channel 0 Interrupt Status Flag is set by hardware when PWM0 down counter reaches zero, software can write 1 to clear this bit to zero.
PWMIF1

PWM Channel 1 Interrupt Status Flag is set by hardware when PWM1 down counter reaches zero, software can write 1 to clear this bit to zero.
PWMIF2

PWM Channel 2 Interrupt Status Flag is set by hardware when PWM2 down counter reaches zero, software can write 1 to clear this bit to zero.
PWMIF3

PWM Channel 3 Interrupt Status Flag is set by hardware when PWM3 down counter reaches zero, software can write 1 to clear this bit to zero.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data