Interrupt Control State Register
| VECTACTIVE | 0 = Thread mode Value > 1 = the exception number for the current executing exception.This is a read only bit. |
| VECTPENDING | Indicates the exception number for the highest priority pending exception. The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions. This is a read only bit. |
| ISRPENDING | Indicates if an external configurable (NVIC generated) interrupt is pending. This is a read only bit. |
| ISRPREEMPT | If set, a pending exception will be serviced on exit from the debug halt state. This is a read only bit. |
| PENDSTCLR | Write 1 to clear a pending SysTick. This is a write only bit. |
| PENDSTSET | Set a pending SysTick. Reads back with current state (1 if Pending, 0 if not). |
| PENDSVCLR | Write 1 to clear a pending PendSV interrupt. This is a write only bit. |
| PENDSVSET | Set a pending PendSV interrupt. This is normally used to request a context switch. Reads back with current state (1 if Pending, 0 if not). |
| NMIPENDSET | Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not). |