Nuvoton /NUC1xx_registers /SPI0 /SPI_CNTRL

Go and Busy Status 1 = In master mode, writing 1 to this bit to start the SPI data transfer; in slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master. 0 = Writing 0 to this bit to stop data transfer if SPI is transferring. During the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. NOTE: All registers should be set before writing 1 to this GO_BUSY bit. The transfer result will be unpredictable if software changes related settings when GO_BUSY bit is 1.

Receive At Negative Edge 1 = The received data input signal is latched at the falling edge of SPICLK. 0 = The received data input signal is latched at the rising edge of SPICLK.

Transmit At Negative Edge 1 = The transmitted data output signal is changed at the falling edge of SPICLK. 0 = The transmitted data output signal is changed at the rising edge of SPICLK.

Transmit Bit Length This field specifies how many bits are transmitted in one transaction. Up to 32 bits can be transmitted. TX_BIT_LEN = 0x01 … 1 bit TX_BIT_LEN = 0x02 … 2 bits … TX_BIT_LEN = 0x1f … 31 bits TX_BIT_LEN = 0x00 … 32 bits

Numbers of Transmit/Receive Word This field specifies how many transmit/receive word numbers should be executed in one transfer. 00 = Only one transmit/receive word will be executed in one transfer. 01 = Two successive transmit/receive words will be executed in one transfer. (burst mode) 10 = Reserved. 11 = Reserved.

LSB First 1 = The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1). 0 = The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the TX_BIT_LEN field).

Clock Polarity 1 = SPICLK idle high. 0 = SPICLK idle low.

Suspend Interval (master only) These four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKP = 0. If CLKP = 1, the interval is from the rising clock edge to the falling clock edge. The default value is 0x0. When TX_NUM = 00b, setting this field has no effect on transfer. The desired suspend interval is obtained according to the following equation: (SP_CYCLE[3:0] + 2)*period of SPI clock SP_CYCLE = 0x0 … 2 SPICLK clock cycle SP_CYCLE = 0x1 … 3 SPICLK clock cycle … SP_CYCLE = 0xe … 16 SPICLK clock cycle SP_CYCLE = 0xf … 17 SPICLK clock cycle

Interrupt Flag 1 = It indicates that the transfer is done. The interrupt flag is set if it was enable. 0 = It indicates that the transfer does not finish yet. NOTE: This bit can be cleared by writing 1 to itself.

Interrupt Enable 1 = Enable MICROWIRE/SPI Interrupt. 0 = Disable MICROWIRE/SPI Interrupt.

SLAVE Mode Indication 1 = Slave mode. 0 = Master mode.

Reorder Mode Select 00 = Disable both byte reorder and byte suspend functions. 01 = Enable byte reorder function and insert a byte suspend interval (2~17 SPICLK cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word). 10 = Enable byte reorder function, but disable byte suspend function. 11 = Disable byte reorder function, but insert a suspend interval (2~17 SPICLK cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word). Byte reorder function is only available if TX_BIT_LEN is defined as 16, 24 and 32.

Two Bits Transfer Mode Active 1 = Enable two-bit transfer mode. 0 = disable two-bit transfer mode. Note that when enable TWOB, the serial transmitted 2-bit data output are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0. Note that when enable TWOB, the setting of TX_NUM must be programmed as 0x00.

Variable Clock Enable (master only) 1 = The serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2. 0 = The serial clock output frequency is fixed and decided only by the value of DIVIDER. Note that when enable this VARCLK_EN bit, the setting of TX_BIT_LEN must be programmed as 0x10 (16 bits mode)