Timer0 Control and Status Register
| PRESCALE | Pre-scale Counter Clock input is divided by PRESCALE+1 before it is fed to the counter. If PRESCALE=0, then there is no scaling. |
| TDR_EN | Data Load Enable When TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting. 1 = Timer Data Register update enable. 0 = Timer Data Register update disable. |
| CTB | Counter Mode Enable Bit (Low Density only) This bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter triggered by raising edge of external pin. 1 = Enable counter mode 0 = Disable counter mode |
| CACT | Timer Active Status Bit (Read only) This bit indicates the up-timer status. 0 = Timer is not active. 1 = Timer is active. |
| CRST | Timer Reset Bit Set this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0. 0 = No effect. 1 = Reset Timer’s 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit. |
| MODE | Timer Operating Mode MODE Timer Operating Mode 00 The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if IE is enabled) and CEN is automatically cleared by hardware. 01 The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if IE is enabled). 10 The timer is operating in the toggle mode. The interrupt signal is generated periodically (if IE is enabled). And the associated signal (tout) is changing back and forth with 50% duty cycle. (This mode only supported in Low Density) 11 The timer is operating in auto-reload counting mode. The associated interrupt signal is generated when TDR = TCMPR (if IE is enabled); however, the 24-bit up-timer counts continuously without reset. (This mode only supported in Low Density) |
| IE | Interrupt Enable Bit 1 = Enable timer Interrupt. 0 = Disable timer Interrupt. If timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR. |
| CEN | Timer Enable Bit 1 = Starts counting 0 = Stops/Suspends counting Note1: In stop status, and then set CEN to 1 will enables the 24-bit up-timer keeps up counting from the last stop counting value. Note2: This bit is auto-cleared by hardware in one-shot mode (MODE[28:27]=00) when the associated timer interrupt is generated (IE[29]=1). |