Baud Rate Divisor Register
| BRD | Baud Rate Divider The field indicated the baud rate divider |
| DIVIDER_X | Divider X The baud rate divider M = X+1. |
| DIV_X_ONE | Divider X equal 1 0 = Divider M = X (the equation of M = X+1, but Divider_X[27:24] must > =8) 1 = Divider M = 1 (the equation of M = 1, but BRD[15:0] must >=3). Mode DIV_X_EN DIV_X_ONE DIVIDER X BRD Baud rate equation 0 Disable 0 B A UART_CLK / [16 * (A+2)] 1 Enable 0 B A UART_CLK/[(B+1)*(A+2)],B must >= 8 2 Enable 1 Don’t Care A UART_CLK / (A+2), A must >=3 |
| DIV_X_EN | Divider X Enable The BRD = Baud Rate Divider, and the baud rate equation is Baud Rate = Clock / [ M * (BRD + 2) ] ; The default value of M is 16. 0 = Disable divider X (the equation of M = 16) 1 = Enable divider X (the equation of M = X+1, but Divider_X[27:24 must > =8). NOTE: When in IrDA mode, this bit must disable. Mode DIV_X_EN DIV_X_ONE DIVIDER X BRD Baud rate equation 0 Disable 0 B A UART_CLK / [16 * (A+2)] 1 Enable 0 B A UART_CLK/[(B+1)*(A+2)],B must >= 8 2 Enable 1 Don’t Care A UART_CLK / (A+2), A must >=3 |