FIFO Control Register.
| RFR | Rx Field Software Reset When Rx_RST is set, all the bytes in the transmit FIFO and Rx internal state machine are cleared. 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit will reset the Rx internal state machine and pointers. Note: This bit will auto clear needs at least 3 UART engine clock cycles. |
| TFR | Tx Field Software Reset When Tx_RST is set, all the bytes in the transmit FIFO and Tx internal state machine are cleared. 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit will reset the Tx internal state machine and pointers. Note: This bit will auto clear needs at least 3 UART engine clock cycles. |
| RFITL | Rx FIFO Interrupt (INT_RDA) Trigger Level When the number of bytes in the receive FIFO equals the RFITL then the RDA_IF will be set (if IER [RDA_IEN] is enable, an interrupt will generated). RFITL INTR_RDA Trigger Level (Bytes) 0000 01 0001 04 0010 08 0011 14 0100 30/14 (High Speed/Normal Speed) 0101 46/14 (High Speed/Normal Speed) 0110 62/14 (High Speed/Normal Speed) others 62/14 (High Speed/Normal Speed) |
| RX_DIS | Receiver Disable register The receiver is disabled or not (set 1 is disable receiver) 1 = Disable Receiver. 0 = Enable Receiver. Note: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed. |
| RTS_TRI_LEV | RTS Trigger Level for Auto-flow Control Use(not available in UART2 channel) RTS_Tri_Lev Trigger Level (Bytes) 0000 01 0001 04 0010 08 0011 14 0100 30/14 (High Speed/Normal Speed) 0101 46/14 (High Speed/Normal Speed) 0110 62/14 (High Speed/Normal Speed) others 62/14 (High Speed/Normal Speed) |