Nuvoton /NUC1xx_registers /UART0 /UA_FSR

Rx overflow Error IF (Read Only) This bit is set when Rx FIFO overflow. If the number of bytes of received data is greater than Rx FIFO(UA_RBR) size, 64/16 bytes of (UA_RBR), this bit will be set. NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.

RS-485 Address Byte Detection Flag (Read Only) (Low Density Only) This bit is set to logic 1 and set UA_ALT_CSR [RS485_ADD_EN] whenever in RS-485 mode the receiver detect any address byte received address byte character (bit9 = 1) bit, and it is reset whenever the CPU writes 1 to this bit. NOTE: This field is used for RS-485 function mode. NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.

Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid “parity bit”, and is reset whenever the CPU writes 1 to this bit. NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.

Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid “stop bit” (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit. NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.

Break Interrupt Flag This bit is set to a logic 1 whenever the received data input(Rx) is held in the “spacing state” (logic 0) for longer than a full word transmission time (that is, the total time of “start bit” + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit. NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.

Rx FIFO pointer (Read Only) This field indicates the Rx FIFO Buffer Pointer. When UART receives one byte from external device, Rx_Pointer increases one. When one byte of Rx FIFO is read by CPU, Rx_Pointer decreases one.

Receiver FIFO Empty (Read Only) This bit initiate Rx FIFO empty or not. When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.

Receiver FIFO Full (Read Only) This bit initiates Rx FIFO full or not. This bit is set when RX_POINTER is equal to 64/16(UART0/UART1), otherwise is cleared by hardware.

TX FIFO Pointer (Read Only) This field indicates the Tx FIFO Buffer Pointer. When CPU write one byte into UA_THR, Tx_Pointer increases one. When one byte of Tx FIFO is transferred to Transmitter Shift Register, Tx_Pointer decreases one.

Transmitter FIFO Empty (Read Only) This bit indicates Tx FIFO empty or not. When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (Tx FIFO not empty).

Transmitter FIFO Full (Read Only) This bit indicates Tx FIFO full or not. This bit is set when Tx_Point is equal to 64/16(UART0/UART1), otherwise is cleared by hardware.

Tx Overflow Error Interrupt Flag (Read Only) If Tx FIFO(UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.

Transmitter Empty Flag (Read Only) Bit is set by hardware when Tx FIFO(UA_THR) is empty and the STOP bit of the last byte has been transmitted. Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed. NOTE: This bit is read only.