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Nuvoton /NUC1xx_registers /UART0 /UA_ISR

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Interpret as UA_ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RDA_IF)RDA_IF 0 (THRE_IF)THRE_IF 0 (RLS_IF)RLS_IF 0 (MODEM_IF)MODEM_IF 0 (TOUT_IF)TOUT_IF 0 (BUF_ERR_IF)BUF_ERR_IF 0 (LIN_RX_BREAK_IF)LIN_RX_BREAK_IF 0 (RDA_INT)RDA_INT 0 (THRE_INT)THRE_INT 0 (RLS_INT)RLS_INT 0 (MODEM_INT)MODEM_INT 0 (TOUT_INT)TOUT_INT 0 (BUF_ERR_INT)BUF_ERR_INT 0 (LIN_RX_BREAK_INT)LIN_RX_BREAK_INT 0 (HW_RLS_IF)HW_RLS_IF 0 (HW_MODEM_IF)HW_MODEM_IF 0 (HW_TOUT_IF)HW_TOUT_IF 0 (HW_BUF_ERR_IF)HW_BUF_ERR_IF 0 (HW_LIN_RX_BREAK_IF)HW_LIN_RX_BREAK_IF 0 (HW_RLS_INT)HW_RLS_INT 0 (HW_MODEM_INT)HW_MODEM_INT 0 (HW_TOUT_INT)HW_TOUT_INT 0 (HW_BUF_ERR_INT)HW_BUF_ERR_INT 0 (HW_LIN_RX_BREAK_INT)HW_LIN_RX_BREAK_INT

Description

Interrupt Status Register.

Fields

RDA_IF

Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the Rx FIFO equals the RFITL then the RDA_IF will be set. If IER[RDA_IEN] is enabled, the RDA interrupt will be generated. NOTE: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL).
THRE_IF

Transmit Holding Register Empty Interrupt Flag (Read Only). This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER[THRE_IEN] is enabled, the THRE interrupt will be generated. NOTE: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
RLS_IF

Receive Line Interrupt Flag (Read Only). This bit is set when the Rx receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If IER[RLS_IEN] is enabled, the RLS interrupt will be generated. NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. NOTE: When in RS-485 function mode, this field include "receiver detect any address byte received address byte character (bit9 = 1’) bit. "
MODEM_IF

MODEM Interrupt Flag (Read Only) (not available in UART2 channel) This bit is set when the CTS pin has state change(DCTSF=1). if UA_IER[Modem_IEN] is enabled, the Modem interrupt will be generated. NOTE: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
TOUT_IF

Time Out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurres in the RX FIFO and the time out counter equal to TOIC. If IER[Tout_IEN] is enabled, the Tout interrupt will be generated. NOTE: This bit is read only and user can read UA_RBR (Rx is in active) to clear it.
BUF_ERR_IF

Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TX_Over_IF or RX_Over_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER[BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated. NOTE: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared.
LIN_RX_BREAK_IF

LIN Bus RX Break Field Detected Flag This bit is set when RX received LIN Break Field. If UA_IER[LIN_RX_BRK_IEN] is enabled the LIN RX Break interrupt will be generated. NOTE: This bit is read only and user can write 1 to clear it.
RDA_INT

Receive Data Available Interrupt Indicator (INT_RDA). This bit is set if RDA_IEN and RDA_IF are both set to 1. 1 = The RDA interrupt is generated. 0 = No RDA interrupt is generated .
THRE_INT

Transmit Holding Register Empty Interrupt Indicator (INT_THRE). This bit is set if THRE_IEN and THRE_IF are both set to 1. 1 = The THRE interrupt is generated. 0 = No THRE interrupt is generated.
RLS_INT

Receive Line Status Interrupt Indicator to (INT_RLS). This bit is set if RLS_IEN and RLS_IF are both set to 1. 1 = The RLS interrupt is generated. 0 = No RLS interrupt is generated.
MODEM_INT

MODEM Status Interrupt Indicator to (INT_MOS). This bit is set if MODEM_IEN and MODEM_IF are both set to 1… 1 = The Modem interrupt is generated. 0 = No Modem interrupt is generated.
TOUT_INT

Time Out Interrupt Indicator (INT_Tout) This bit is set if TOUT_IEN and TOUT_IF are both set to 1. 1 = The Tout interrupt is generated. 0 = No Tout interrupt is generated.
BUF_ERR_INT

Buffer Error Interrupt Indicator (INT_Buf_err) This bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1. 1 = The buffer error interrupt is generated. 0 = No buffer error interrupt is generated.
LIN_RX_BREAK_INT

LIN Bus Rx Break Field Detected Interrupt Indicator This bit is set if LIN_RX_BRK_IEN and LIN_RX_BREAK_IF are both set to 1. 1 = The LIN RX Break interrupt is generated. 0 = No LIN RX Break interrupt is generated.
HW_RLS_IF

In DMA mode, Receive Line Status Flag (Read Only) This bit is set when the Rx receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If IER[RLS_IEN] is enabled, the RLS interrupt will be generated. NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
HW_MODEM_IF

In DMA mode, MODEM Interrupt Flag (Read Only) (not available in UART2 channel) This bit is set when the CTS pin has state change(DCTSF=1). if IER[Modem_IEN] is enabled, the Modem interrupt will be generated. NOTE: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
HW_TOUT_IF

In DMA mode, Time out Interrupt Flag (Read Only) This bit is set when the Rx FIFO is not empty and no activities occurres in the Rx FIFO and the time out counter equal to TOIC. If IER[Tout_IEN] is enabled, the Tout interrupt will be generated. NOTE: This bit is read only and user can read UA_RBR (Rx is in active) to clear it.
HW_BUF_ERR_IF

In DMA mode, Buffer Error Interrupt Flag (Read Only) This bit is set when the Tx or Rx FIFO overflows (Tx_Over_IF or Rx_Over_IF is set). When Buf_Err_IF is set, the transfer maybe is not correct. If IER[Buf_Err_IEN] is enabled, the buffer error interrupt will be generated. NOTE: This bit is cleared when both Tx_Over_IF and Rx_Over_IF are cleared.
HW_LIN_RX_BREAK_IF

In DMA mode, LIN Bus Rx Break Field Detect Interrupt Flag This bit is set when Rx received LIN Break Field. If IER[LIN_RX_BRK_IEN] is enabled the LIN RX Break interrupt will be generated. NOTE: This bit is read only and user can write 1 to clear it.
HW_RLS_INT

In DMA mode, Receive Line Status Interrupt Indicator (INT_RLS). This bit is set if RLS_IEN and HW_RLS_IF are both set to 1. 1 = The RLS interrupt is generated in DMA mode. 0 = No RLS interrupt is generated in DMA mode.
HW_MODEM_INT

In DMA mode, MODEM Status Interrupt Indicator (INT_MOS)(not available in UART2 channel). This bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1. 1 = The Modem interrupt is generated in DMA mode. 0 = No Modem interrupt is generated in DMA mode.
HW_TOUT_INT

In DMA mode, Time Out Interrupt Indicator (INT_Tout) This bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1. 1 = The Tout interrupt is generated in DMA mode. 0 = No Tout interrupt is generated in DMA mode.
HW_BUF_ERR_INT

In DMA mode, Buffer Error Interrupt Indicator(INT_Buf_err) This bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1. 1 = The buffer error interrupt is generated in DMA mode. 0 = No buffer error interrupt is generated in DMA mode.
HW_LIN_RX_BREAK_INT

In DMA mode, LIN Bus Rx Break Field Detected Interrupt Indicator This bit is set if LIN_RX_BRK_IEN and HW_LIN_RX_BREAK_IF are both set to 1. 1 = The LIN RX Break interrupt is generated in DMA mode. 0 = No LIN RX Break interrupt is generated in DMA mode.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data