Line Control Register.
| WLS | Word Length Select WLS[1:0] Character length 00 5 bits 01 6 bits 10 7 bits 11 8 bits |
| NSB | Number of “STOP bit” 0= One “STOP bit” is generated in the transmitted data 1= One and a half “STOP bit” is generated in the transmitted data when 5-bit word length is selected; Two “STOP bit” is generated when 6-, 7- and 8-bit word length is selected. |
| PBE | Parity Bit Enable 0 = Parity bit is not generated (transmit data) or checked (receive data) during transfer. 1 = Parity bit is generated or checked between the “last data word bit” and “stop bit” of the serial data. |
| EPE | Even Parity Enable 0 = Odd number of logic 1’s are transmitted or checked in the data word and parity bits. 1 = Even number of logic 1’s are transmitted or checked in the data word and parity bits. This bit has effect only when bit 3 (parity bit enable) is set. |
| SPE | Stick Parity Enable 0 = Disable stick parity 1 = When bits PBE , EPE and SPE are set, the parity bit is transmitted and checked as cleared. When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as set. |
| BCB | Break Control Bit When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. |