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RISC-V /misa

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Interpret as misa

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (A)A0 (B)B0 (C)C0 (D)D0 (E)E0 (F)F0 (G)G0 (H)H0 (I)I0 (J)J0 (K)K0 (L)L0 (M)M0 (N)N0 (O)O0 (P)P0 (Q)Q0 (R)R0 (S)S0 (T)T0 (U)U0 (V)V0 (W)W0 (X)X0 (Y)Y0 (Z)Z0mxl

Description

Machine ISA register (MXLEN=32)

Fields

A

Atomic instructions
B

Bit manipulation
C

Compressed instructions
D

Double-precision floating-point
E

RV32E/64E base ISA
F

Single-precision floating-point
G

Reserved
H

Hypervisor extension
I

RV32I/64I/128I base ISA
J

Dynamically Translated Languages
K

Reserved
L

Decimal floating-point
M

Integer multiplication and division
N

User-Level Interrupts
O

Reserved
P

Packed-SIMD instructions
Q

Quad-precision floating-point
R

Reserved
S

Supervisor mode
T

Transactional memory
U

User mode
V

Vector instructions
W

Reserved
X

Non-standard extensions present
Y

Reserved
Z

Reserved
mxl

XLEN

1 (RV32): 32-bit

2 (RV64): 64-bit

3 (RV128): 128-bit