STMicroelectronics /STM32F301 /ADC /CSR

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Interpret as CSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ADRDY_MST)ADRDY_MST 0 (EOSMP_MST)EOSMP_MST 0 (EOC_MST)EOC_MST 0 (EOS_MST)EOS_MST 0 (OVR_MST)OVR_MST 0 (JEOC_MST)JEOC_MST 0 (JEOS_MST)JEOS_MST 0 (AWD1_MST)AWD1_MST 0 (AWD2_MST)AWD2_MST 0 (AWD3_MST)AWD3_MST 0 (JQOVF_MST)JQOVF_MST 0 (ADRDY_SLV)ADRDY_SLV 0 (EOSMP_SLV)EOSMP_SLV 0 (EOC_SLV)EOC_SLV 0 (EOS_SLV)EOS_SLV 0 (OVR_SLV)OVR_SLV 0 (JEOC_SLV)JEOC_SLV 0 (JEOS_SLV)JEOS_SLV 0 (AWD1_SLV)AWD1_SLV 0 (AWD2_SLV)AWD2_SLV 0 (AWD3_SLV)AWD3_SLV 0 (JQOVF_SLV)JQOVF_SLV

Description

ADC Common status register

Fields

ADRDY_MST

Master ADC ready

EOSMP_MST

End of Sampling phase flag of the master ADC

EOC_MST

End of regular conversion of the master ADC

EOS_MST

End of regular sequence flag of the master ADC

OVR_MST

Overrun flag of the master ADC

JEOC_MST

End of injected conversion flag of the master ADC

JEOS_MST

End of injected sequence flag of the master ADC

AWD1_MST

Analog watchdog 1 flag of the master ADC

AWD2_MST

Analog watchdog 2 flag of the master ADC

AWD3_MST

Analog watchdog 3 flag of the master ADC

JQOVF_MST

Injected Context Queue Overflow flag of the master ADC

ADRDY_SLV

Slave ADC ready

EOSMP_SLV

End of Sampling phase flag of the slave ADC

EOC_SLV

End of regular conversion of the slave ADC

EOS_SLV

End of regular sequence flag of the slave ADC

OVR_SLV

Overrun flag of the slave ADC

JEOC_SLV

End of injected conversion flag of the slave ADC

JEOS_SLV

End of injected sequence flag of the slave ADC

AWD1_SLV

Analog watchdog 1 flag of the slave ADC

AWD2_SLV

Analog watchdog 2 flag of the slave ADC

AWD3_SLV

Analog watchdog 3 flag of the slave ADC

JQOVF_SLV

Injected Context Queue Overflow flag of the slave ADC

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