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STMicroelectronics /STM32F301 /ADC /ISR

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Interpret as ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ADRDY)ADRDY 0 (EOSMP)EOSMP 0 (EOC)EOC 0 (EOS)EOS 0 (OVR)OVR 0 (JEOC)JEOC 0 (JEOS)JEOS 0 (AWD1)AWD1 0 (AWD2)AWD2 0 (AWD3)AWD3 0 (JQOVF)JQOVF

Description

ADC interrupt and status register

Fields

ADRDY

ADC ready
EOSMP

End of sampling flag
EOC

End of conversion flag
EOS

End of regular sequence flag
OVR

ADC overrun
JEOC

Injected channel end of conversion flag
JEOS

Injected channel end of sequence flag
AWD1

Analog watchdog 1 flag
AWD2

Analog watchdog 2 flag
AWD3

Analog watchdog 3 flag
JQOVF

Injected context queue overflow

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data