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STMicroelectronics /STM32F3x4 /ADC_Common /ADC1_CCR

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Interpret as ADC1_CCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DUAL0DELAY0 (DMACFG)DMACFG 0MDMA 0CKMODE 0 (VREFEN)VREFEN 0 (TSEN)TSEN 0 (VBATEN)VBATEN

Description

ADC common control register

Fields

DUAL

Dual ADC mode selection
DELAY

Delay between 2 sampling phases
DMACFG

DMA configuration (for dual ADC mode)
MDMA

Direct memory access mode for dual ADC mode
CKMODE

ADC clock mode
VREFEN

VREFINT enable
TSEN

Temperature sensor enable
VBATEN

VBAT enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data