IFCR

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Interpret as IFCR

DMA interrupt flag clear register (DMA_IFCR)

CGIF1	Channel 1 Global interrupt clear
CTCIF1	Channel 1 Transfer Complete clear
CHTIF1	Channel 1 Half Transfer clear
CTEIF1	Channel 1 Transfer Error clear
CGIF2	Channel 2 Global interrupt clear
CTCIF2	Channel 2 Transfer Complete clear
CHTIF2	Channel 2 Half Transfer clear
CTEIF2	Channel 2 Transfer Error clear
CGIF3	Channel 3 Global interrupt clear
CTCIF3	Channel 3 Transfer Complete clear
CHTIF3	Channel 3 Half Transfer clear
CTEIF3	Channel 3 Transfer Error clear
CGIF4	Channel 4 Global interrupt clear
CTCIF4	Channel 4 Transfer Complete clear
CHTIF4	Channel 4 Half Transfer clear
CTEIF4	Channel 4 Transfer Error clear
CGIF5	Channel 5 Global interrupt clear
CTCIF5	Channel 5 Transfer Complete clear
CHTIF5	Channel 5 Half Transfer clear
CTEIF5	Channel 5 Transfer Error clear
CGIF6	Channel 6 Global interrupt clear
CTCIF6	Channel 6 Transfer Complete clear
CHTIF6	Channel 6 Half Transfer clear
CTEIF6	Channel 6 Transfer Error clear
CGIF7	Channel 7 Global interrupt clear
CTCIF7	Channel 7 Transfer Complete clear
CHTIF7	Channel 7 Half Transfer clear
CTEIF7	Channel 7 Transfer Error clear

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