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STMicroelectronics /STM32F3x8 /RCC /APB2RSTR

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Interpret as APB2RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYSCFGRST)SYSCFGRST 0 (ADCRST)ADCRST 0 (SPI1RST)SPI1RST 0 (USART1RST)USART1RST 0 (TIM15RST)TIM15RST 0 (TIM16RST)TIM16RST 0 (TIM17RST)TIM17RST 0 (TIM19RST)TIM19RST 0 (SDAD1RST)SDAD1RST 0 (SDAD2RST)SDAD2RST 0 (SDAD3RST)SDAD3RST

Description

APB2 peripheral reset register (RCC_APB2RSTR)

Fields

SYSCFGRST

SYSCFG and COMP reset
ADCRST

ADC interface reset
SPI1RST

SPI 1 reset
USART1RST

USART1 reset
TIM15RST

TIM15 timer reset
TIM16RST

TIM16 timer reset
TIM17RST

TIM17 timer reset
TIM19RST

TIM19 timer reset
SDAD1RST

SDADC1 (Sigma delta ADC 1) reset
SDAD2RST

SDADC2 (Sigma delta ADC 2) reset
SDAD3RST

SDADC3 (Sigma delta ADC 3) reset

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data