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STMicroelectronics /STM32F3x8 /SYSCFG_COMP_OPAMP /SYSCFG_CFGR2

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Interpret as SYSCFG_CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LOCUP_LOCK)LOCUP_LOCK 0 (SRAM_PARITY_LOCK)SRAM_PARITY_LOCK 0 (PVD_LOCK)PVD_LOCK 0 (BYP_ADD_PAR)BYP_ADD_PAR 0 (SRAM_PEF)SRAM_PEF

Description

configuration register 2

Fields

LOCUP_LOCK

Cortex-M0 LOCKUP bit enable bit
SRAM_PARITY_LOCK

SRAM parity lock bit
PVD_LOCK

PVD lock enable bit
BYP_ADD_PAR

Bypass address bit 29 in parity calculation
SRAM_PEF

SRAM parity flag

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data