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STMicroelectronics /STM32F410 /RCC /APB1RSTR

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Interpret as APB1RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM5RST)TIM5RST 0 (TIM6RST)TIM6RST 0 (LPTIM1RST)LPTIM1RST 0 (WWDGRST)WWDGRST 0 (SPI2RST)SPI2RST 0 (UART2RST)UART2RST 0 (I2C1RST)I2C1RST 0 (I2C2RST)I2C2RST 0 (I2C4RST)I2C4RST 0 (PWRRST)PWRRST 0 (DACRST)DACRST

Description

APB1 peripheral reset register

Fields

TIM5RST

TIM5 reset
TIM6RST

TIM6 reset
LPTIM1RST

LPTIM1 reset
WWDGRST

Window watchdog reset
SPI2RST

SPI 2 reset
UART2RST

USART 2 reset
I2C1RST

I2C 1 reset
I2C2RST

I2C 2 reset
I2C4RST

I2C4 reset
PWRRST

Power interface reset
DACRST

DAC reset

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data