DMA2D control register
| START | Start This bit can be used to launch the DMA2D according to the parameters loaded in the various configuration registers. This bit is automatically reset by the following events: ** At the end of the transfer ** When the data transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** When a data transfer error occurs ** When the data transfer has not started due to a configuration error or another transfer operation already ongoing (automatic CLUT loading). |
| SUSP | Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when the START bit is reset. |
| ABORT | Abort This bit can be used to abort the current transfer. This bit is set by software and is automatically reset by hardware when the START bit is reset. |
| TEIE | Transfer error interrupt enable This bit is set and cleared by software. |
| TCIE | Transfer complete interrupt enable This bit is set and cleared by software. |
| TWIE | Transfer watermark interrupt enable This bit is set and cleared by software. |
| CAEIE | CLUT access error interrupt enable This bit is set and cleared by software. |
| CTCIE | CLUT transfer complete interrupt enable This bit is set and cleared by software. |
| CEIE | Configuration Error Interrupt Enable This bit is set and cleared by software. |
| MODE | DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing. |