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STMicroelectronics /STM32F730 /USBPHYC /PLL1

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Interpret as PLL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PLL1EN)PLL1EN 0PLL1SEL

Description

USBPHYC PLL1 control register

Fields

PLL1EN

Enable the PLL1 inside PHY
PLL1SEL

: Controls the PHY PLL1 input clock frequency selection

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data