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STMicroelectronics /STM32F750 /TIM1 /BDTR

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Interpret as BDTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DTG0LOCK 0 (OSSI)OSSI 0 (OSSR)OSSR 0 (BKE)BKE 0 (BKP)BKP 0 (AOE)AOE 0 (MOE)MOE

Description

break and dead-time register

Fields

DTG

Dead-time generator setup
LOCK

Lock configuration
OSSI

Off-state selection for Idle mode
OSSR

Off-state selection for Run mode
BKE

Break enable
BKP

Break polarity
AOE

Automatic output enable
MOE

Main output enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data