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STMicroelectronics /STM32F7x3 /RCC /AHB2LPENR

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Interpret as AHB2LPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AESLPEN)AESLPEN 0 (RNGLPEN)RNGLPEN 0 (OTGFSLPEN)OTGFSLPEN

Description

AHB2 peripheral clock enable in low power mode register

Fields

AESLPEN

AES module clock enable during Sleep mode
RNGLPEN

Random number generator clock enable during Sleep mode
OTGFSLPEN

USB OTG FS clock enable during Sleep mode

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data