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STMicroelectronics /STM32F7x3 /TIM13 /CCMR1_Output

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Interpret as CCMR1_Output

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CC1S 0 (OC1FE)OC1FE 0 (OC1PE)OC1PE 0OC1M0 (OC1M_3)OC1M_3

Description

capture/compare mode register 1 (output mode)

Fields

CC1S

Capture/Compare 1 selection
OC1FE

Output Compare 1 fast enable
OC1PE

Output Compare 1 preload enable
OC1M

Output Compare 1 mode
OC1M_3

Output Compare 1 mode - bit 3

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data