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STMicroelectronics /STM32G030 /TIM1 /TISEL

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Interpret as TISEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TI1SEL3_0 0TI2SEL3_0 0TI3SEL3_0 0TI4SEL3_0

Description

TIM1 timer input selection register

Fields

TI1SEL3_0

selects TI1[0] to TI1[15] input
TI2SEL3_0

selects TI2[0] to TI2[15] input
TI3SEL3_0

selects TI3[0] to TI3[15] input
TI4SEL3_0

selects TI4[0] to TI4[15] input

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data