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STMicroelectronics /STM32G031 /RCC /APBRSTR1

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Interpret as APBRSTR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM2RST)TIM2RST 0 (TIM3RST)TIM3RST 0 (SPI2RST)SPI2RST 0 (USART2RST)USART2RST 0 (LPUART1RST)LPUART1RST 0 (I2C1RST)I2C1RST 0 (I2C2RST)I2C2RST 0 (DBGRST)DBGRST 0 (PWRRST)PWRRST 0 (LPTIM2RST)LPTIM2RST 0 (LPTIM1RST)LPTIM1RST

Description

APB peripheral reset register 1

Fields

TIM2RST

TIM2 timer reset
TIM3RST

TIM3 timer reset
SPI2RST

SPI2 reset
USART2RST

USART2 reset
LPUART1RST

LPUART1 reset
I2C1RST

I2C1 reset
I2C2RST

I2C2 reset
DBGRST

Debug support reset
PWRRST

Power interface reset
LPTIM2RST

Low Power Timer 2 reset
LPTIM1RST

Low Power Timer 1 reset

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data