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STMicroelectronics /STM32G031 /SYSCFG /CFGR2

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Interpret as CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LOCKUP_LOCK)LOCKUP_LOCK 0 (SRAM_PARITY_LOCK)SRAM_PARITY_LOCK 0 (PVD_LOCK)PVD_LOCK 0 (ECC_LOCK)ECC_LOCK 0 (SRAM_PEF)SRAM_PEF 0 (PA1_CDEN)PA1_CDEN 0 (PA3_CDEN)PA3_CDEN 0 (PA5_CDEN)PA5_CDEN 0 (PA6_CDEN)PA6_CDEN 0 (PA13_CDEN)PA13_CDEN 0 (PB0_CDEN)PB0_CDEN 0 (PB1_CDEN)PB1_CDEN 0 (PB2_CDEN)PB2_CDEN

Description

SYSCFG configuration register 1

Fields

LOCKUP_LOCK

Cortex-M0+ LOCKUP bit enable bit
SRAM_PARITY_LOCK

SRAM parity lock bit
PVD_LOCK

PVD lock enable bit
ECC_LOCK

ECC error lock bit
SRAM_PEF

SRAM parity error flag
PA1_CDEN

PA1_CDEN
PA3_CDEN

PA3_CDEN
PA5_CDEN

PA5_CDEN
PA6_CDEN

PA6_CDEN
PA13_CDEN

PA13_CDEN
PB0_CDEN

PB0_CDEN
PB1_CDEN

PB1_CDEN
PB2_CDEN

PB2_CDEN

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data