DBG_STANDBY=B_0x0, DBG_STOP=B_0x0
DBG configuration register
| DBG_STOP | Debug Stop mode Debug options in Stop mode. Upon Stop mode exit, the software must re-establish the desired clock configuration. 0 (B_0x0): All clocks disabled, including FCLK and HCLK. Upon Stop mode exit, the CPU is clocked by the HSI internal RC oscillator. 1 (B_0x1): FCLK and HCLK running, derived from the internal RC oscillator remaining active. If Systick is enabled, it may generate periodic interrupt and wake up events. |
| DBG_STANDBY | Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode. 0 (B_0x0): Digital part powered. From software point of view, exiting Standby and Shutdown modes is identical as fetching reset vector (except for status bits indicating that the MCU exits Standby) 1 (B_0x1): Digital part powered and FCLK and HCLK running, derived from the internal RC oscillator remaining active. The MCU generates a system reset so that exiting Standby and Shutdown has the same effect as starting from reset. |