CC3S=B_0x0, CC4S=B_0x0
capture/compare mode register 2 (output mode)
| CC3S | Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0â in TIMx_CCER). 0 (B_0x0): CC3 channel is configured as output 1 (B_0x1): CC3 channel is configured as input, IC3 is mapped on TI3 2 (B_0x2): CC3 channel is configured as input, IC3 is mapped on TI4 3 (B_0x3): CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) |
| OC3FE | Output compare 3 fast enable Refer to OC1FE description. |
| OC3PE | Output compare 3 preload enable Refer to OC1PE description. |
| OC3M1 | Output compare 3 mode Refer to OC1M[3:0] description. |
| OC3CE | Output compare 3 clear enable Refer to OC1CE description. |
| CC4S | Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0â in TIMx_CCER). 0 (B_0x0): CC4 channel is configured as output 1 (B_0x1): CC4 channel is configured as input, IC4 is mapped on TI4 2 (B_0x2): CC4 channel is configured as input, IC4 is mapped on TI3 3 (B_0x3): CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) |
| OC4FE | Output compare 4 fast enable Refer to OC1FE description. |
| OC4PE | Output compare 4 preload enable Refer to OC1PE description. |
| OC4M1 | Output compare 4 mode Refer to OC3M[3:0] description. |
| OC4CE | Output compare 4 clear enable Refer to OC1CE description. |
| OC3M2 | Output compare 3 mode Refer to OC1M[3:0] description. |
| OC4M2 | Output compare 4 mode Refer to OC3M[3:0] description. |