URS=B_0x0, UDIS=B_0x0, CEN=B_0x0, ARPE=B_0x0, UIFREMAP=B_0x0, CKD=B_0x0, OPM=B_0x0
control register 1
| CEN | Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 (B_0x0): Counter disabled 1 (B_0x1): Counter enabled |
| UDIS | Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values. 0 (B_0x0): UEV enabled. An UEV is generated by one of the following events: 1 (B_0x1): UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set. |
| URS | Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit 0 (B_0x0): Any of the following events generate an UEV if enabled: 1 (B_0x1): Only counter overflow generates an UEV if enabled. |
| OPM | One-pulse mode 0 (B_0x0): Counter is not stopped on the update event 1 (B_0x1): Counter stops counting on the next update event (clearing the CEN bit). |
| ARPE | Auto-reload preload enable 0 (B_0x0): TIMx_ARR register is not buffered 1 (B_0x1): TIMx_ARR register is buffered |
| CKD | Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx), 0 (B_0x0): tDTS = tCK_INT 1 (B_0x1): tDTS = 2 Ã tCK_INT 2 (B_0x2): tDTS = 4 Ã tCK_INT |
| UIFREMAP | UIF status bit remapping 0 (B_0x0): No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1 (B_0x1): Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. |