OIS1=B_0x0, CCUS=B_0x0, CCPC=B_0x0, OIS1N=B_0x0, CCDS=B_0x0
control register 2
| CCPC | Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 (B_0x0): CCxE, CCxNE and OCxM bits are not preloaded 1 (B_0x1): CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. |
| CCUS | Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 0 (B_0x0): When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 1 (B_0x1): When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. |
| CCDS | Capture/compare DMA selection 0 (B_0x0): CCx DMA request sent when CCx event occurs 1 (B_0x1): CCx DMA requests sent when update event occurs |
| OIS1 | Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1 (B_0x1): OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 |
| OIS1N | Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): OC1N=0 after a dead-time when MOE=0 1 (B_0x1): OC1N=1 after a dead-time when MOE=0 |