DBA=B_0x0, DBL=B_0x0
DMA control register
| DBA | DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: … Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 0 (B_0x0): TIMx_CR1 1 (B_0x1): TIMx_CR2 2 (B_0x2): TIMx_SMCR |
| DBL | DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). … 0 (B_0x0): 1 transfer, 1 (B_0x1): 2 transfers, 2 (B_0x2): 3 transfers, 17 (B_0x11): 18 transfers. |