CED=B_0x0, RNGEN=B_0x0, IE=B_0x0
control register
| RNGEN | True random number generator enable 0 (B_0x0): True random number generator is disabled. Analog noise sources are powered off and logic clocked by the RNG clock is gated. 1 (B_0x1): True random number generator is enabled. |
| IE | Interrupt Enable 0 (B_0x0): RNG Interrupt is disabled 1 (B_0x1): RNG Interrupt is enabled. An interrupt is pending as soon as DRDY=‘1’, SEIS=‘1’ or CEIS=1 in the RNG_SR register. |
| CED | Clock error detection The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, i.e. to enable or disable CED the RNG must be disabled. 0 (B_0x0): Clock error detection is enable 1 (B_0x1): Clock error detection is disable |